When developing chips it is essential that they get verified thoroughly because it is very hard or impossible to fix them once they have been manufactured. In this class, you will learn how to program verification environments that verify chip functionality efficiently, as well as understand and leverage automation such as constrained random test generation and improve code reuse leveraging a standardized methodology.
This course will teach you how to think like a verification engineer. It will show the software development aspects you need to know to ensure chips are working as expected. You will learn how to implement verification environments.
Programming experience including object-oriented programming. Data & Control structure.
This course is developed by Cadence Design Systems, a global leader in electronic design automation. Cadence® software, hardware, IP, and services help customers around the world to overcome a range of technical and economic hurdles.
Lesson 1: Introduction to Hardware Verification
Lesson 2: Basic stimulus modeling and generation
Lesson 3: Interfacing to the Hardware Model
Lesson 4: Monitoring and Functional Coverage
Lesson 5: Checking
Lesson 6: Aspect Oriented Programming
Lesson 7: Reuse Methodology
Lesson 8: Debugging
Lesson 9: Conclusion and Exam
This class is self paced. You can begin whenever you like and then follow your own pace. It’s a good idea to set goals for yourself to make sure you stick with the course.
This class will always be available!
Take a look at the “Class Summary,” “What Should I Know,” and “What Will I Learn” sections above. If you want to know more, just enroll in the course and start exploring.
Yes! The point is for you to learn what YOU need (or want) to learn. If you already know something, feel free to skip ahead. If you ever find that you’re confused, you can always go back and watch something that you skipped.
It’s completely free! If you’re feeling generous, we would love to have you contribute your thoughts, questions, and answers to the course discussion forum.
Collaboration is a great way to learn. You should do it! The key is to use collaboration as a way to enhance learning, not as a way of sharing answers without understanding them.
Udacity classes are a little different from traditional courses. We intersperse our video segments with interactive questions. There are many reasons for including these questions: to get you thinking, to check your understanding, for fun, etc... But really, they are there to help you learn. They are NOT there to evaluate your intelligence, so try not to let them stress you out.
Learn actively! You will retain more of what you learn if you take notes, draw diagrams, make notecards, and actively try to make sense of the material.
Member of the Product Expert Team in the Functional Verification R&D group of Cadence Design Systems, a leading global Electronic Design Automation company. My primary focus area is the Specman/e and UVM Multi-language solution. I have 10 years of verification experience spanning from an AE to AE Manager to Solutions Architect.
Axel Scherer is a senior engineer and manager with over 10 years of experience building new markets and innovating technical products. Currently, Axel is leading a team for Testbenches and Verification Methodologies in the Functional Verification R&D group at Cadence Design Systems, a leading global Electronic Design Automation company. Axel's work centers on advanced verification on various technologies spanning formal equivalence checking, model checking, assertion-based verification and test bench simulation. He is a passionate and innovative leader with a proven track record of motivating and enabling global teams to succeed.