GT - Embedded Systems

Course Information

P1L1: Review of Computer Architecture

P1L2: Review of VLIW

P1L3: Introduction to ISA

P1L4: Datapaths

P1L5: Registers and Memory

P1L6: Branches

P2L1: Compiler Frontend

P2L2: Control-Flow Graphs

P3L1: Liveness Analysis

P3L1: Register Allocation

P3L2: Energy Opt. Post-pass Reg. Alloc.

P3L3: Differential Reg Allocation

P3L4: Storage Assignment Optimizations

P3L5: Framework for Parallelizing LD ST

P4L1: Network Processors

P4L2: Resolving Register Bank Conflicts

P4L3: Balancing Register Allocations

P3L4: Instruction Selection