Individual stages of the processor have the following latencies:
If the processor is pipelined, each pipeline latch adds a latency of 20ps to the stage that precedes it - this is a so-called “setup latency”, where the signals need to be stable at the input of the latch for some amount of time before they can be latched correctly at the end of the cycle.
If this processor is to be implemented with a 6-stage pipeline, but the design effort and time-to-market are such that there is only enough time to split one of the five existing stages into two new stages, which stage would you chose to split and why?
MEM stage, it has the longest latency. Splitting any other stage does not improve cycle time.