Individual stages of the processor have the following latencies:
If the processor is pipelined, each pipeline latch adds a latency of 20ps to the stage that precedes it - this is a so-called “setup latency”, where the signals need to be stable at the input of the latch for some amount of time before they can be latched correctly at the end of the cycle.
What is the clock cycle time if we implement this processor using a 5-stage pipeline?
Solution: The clock cycle time is the latency of the slowest stage plus one latch latency. The longest-latency stage is MEM, so we have 260ps.