ud233/Problem Set Solutions/Pipelining/Problem 1 is ...
Individual stages of the processor have the following latencies:
If the processor is pipelined, each pipeline latch adds a latency of 20ps to the stage that precedes it - this is a so-called “setup latency”, where the signals need to be stable at the input of the latch for some amount of time before they can be latched correctly at the end of the cycle. What is the clock cycle time if we implement this processor using a single-cycle approach. In this approach, no pipeline is used, and in each cycle one instruction is executed from start (IF) to finish (WB).
The clock cycle time is the sum of execution times for all stages: 700ps.