Sample Final/Problem03

Problem 3. [10 points] Cache Coherence

A shared-memory bus-based multiprocessor has two processors. Each processor has a direct-mapped L1 cache, with only sixteen 256-byte blocks in each cache. All addresses in this problem are physical addresses, and all caches are physically indexed and tagged. The MESI coherence protocol is used in this multiprocessor. The current state of the two caches is:

table1.jpg

The next access is on P0, which executes SB (store byte) to address 0xFFFFFCFF.

[1 point] Does this access result in a bus broadcast? (Yes or No)

[1 point] What is the new content of row C in P0’s and P1’s caches?

table2.jpg

The next access is on P1, which executes SB (store byte) to address 0xFFFFF5FF.

[1 point] Does this access result in a bus broadcast? (Yes or No)

[1 point] What is the new content of row 5 in P0’s and P1’s caches?

table3.jpg

The next access is on P1, which executes LB (load byte) to address 0xFFFFF3FF.

[1 point] Does this access result in a bus broadcast? (Yes or No)

[1 point] What is the new content of row 3 in P0’s and P1’s caches?

table4.jpg

The next access is on P0, which executes SB (load byte) to address 0xFFFFFD00.

[1 point] Does this access result in a bus broadcast? (Yes or No)

[1 point] What is the new content of row D in P0’s and P1’s caches?

table5.jpg

The next access is on P0, which executes SB (load byte) to address 0xFFFFF700.

[1 point] Does this access result in a bus broadcast? (Yes or No)

[1 point] What is the new content of row 7 in P0’s and P1’s caches?

table7.jpg