Sample Final/Problem02

Problem 2. [10 points] Caches

The processor has a 32Kbyte, 32-way set associative, write-back, write-allocate, virtually indexed, physically-tagged L1 cache with 64-byte blocks. The system uses 32-bit virtual and physical addresses, with 4K byte pages.

(A) [2 points] Can we overlap virtual-to-physical address translation with the L1 cache access? Explain you answer.

(B) [2 points] Each time the processor accesses the cache, what is the number of tag comparisons that are needed to determine if the access is a cache hit?

(C) [2 points] If the processor reads memory at virtual address 0x00001234 (physical address 0xFFFF1234), what is the index that is used to access the cache?

(D) [2 points] If the processor reads memory at virtual address 0x00001234 (physical address 0xFFFF1234), what is the tag that is used by the cache to determine if the access is a cache hit?

(E) [2 points] What would be the main argument in favor of changing this cache to make it virtually-tagged?