Using the information from Problem 1 answer the following question.
In order to increase the clock frequency from 500 MHz to 600 Mhz, a designer splits the IF-stage into two stages, IF1 and IF2. This makes it easier for the instruction cache to deliver instructions in time. This also affects the branch penalties for the branch prediction unit as follows:
NT/PNT: 0 cycles T/PT: 2 cycles NT/PT, T/PNT: 3 cycles
How much faster is this new processor than the previous that runs on 500 MHz?
Propose a solution to reduce the average branch penalty even further.
The new processor with higher clock frequency is thus only 8.9% faster than the old even though the clock frequency has been increased by 20%. The sole reason for this is the branch hazards.
A branch target buffer can be used in the IF-stage. The branch penalty for correctly predicted branches will then be 0.
This problem was adapted from: "Exercises for Computer Architecture", Anders Ardo, Lund University