Assume a processor with a standard five-stage pipeline (IF, ID, EX, MEM, WB) and a branch prediction unit (a branch history table) in the ID-stage. Branch resolution is performed in the EX-stage. There are four cases for conditional branches: The branch is not taken and correctly predicted as not taken (NT/PNT) The branch is not taken and predicted as taken (NT/PT) The branch is taken and predicted as not taken (T/PNT) The branch is taken and correctly predicted as taken (T/PT)
Suppose that the branch penalties with this design are: NT/PNT: 0 cycles T/PT: 1 cycle NT/PT, T/PNT: 2 cycles
The CPI equation can be modified to account for the performance of the branch prediction unit:
Use the equation from the previous quiz page to calculate the average CPI for the processor assuming a base CPI of 1.2. Assume 20% conditional branches (disregard from other branches) and that 65% of these are taken on average. Assume further that the branch prediction unit mispredicts 12% of the conditional branches.
This problem was adapted from: "Exercises for Computer Architecture", Anders Ardo, Lund University