Pipelining/Problem 5b

Consider an unpipelined processor. Assume that it has 1-ns clock cycle and that it uses 4 cycles for ALU operations and 5 cycles for branches and 4 cycles for memory operations. Assume that the relative frequencies of these operations are 50 %, 35 % and 15 % respectively. Suppose that due to clock skew and set up, pipelining the processor adds 0.15 ns of overhead to the clock. Ignoring any latency impact, how much speed up in the instruction execution rate will we gain from a pipeline?


The average instruction execution time on an unpipelined processor is clockcycle

Avg:CPI = 1ns ((0:5 4) + (0:35 5) + (0:15 4)) = 4:35ns

The avg. instruction execution time on pipelined processor is = 1ns + 0:15ns = 1:15ns

So speed up = 4:35=1:15 = 3:78