Use the following code fragment:

 Loop: LD R1, 0(R2) 
       DADDI R1, R1, #1 
       SD 0(R2), R1 
       DADDI R2, R2, #4 
       DSUB R4, R3, R2 
       BNEZ R4, Loop

Show the timing of this instruction sequence for a 5 stage pipeline along with the number of cycles required to execute one iteration of the loop with no forwarding. Assume registers can be written and read in the same cycle, during writeback. (The number of cycles for the execution of one iteration of the loop ends after the EX stage of BNEZ instruction)


Number of cycles required = 16

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