Individual stages of the processor have the following latencies:
If the processor is pipelined, each pipeline latch adds a latency of 20ps to the stage that precedes it - this is a so-called “setup latency”, where the signals need to be stable at the input of the latch for some amount of time before they can be latched correctly at the end of the cycle.
What is the speedup of the pipelined processor (from Problem 2) over a single-cycle processor (Problem 1) if the single-cycle processor has a CPI of 1 and the pipelined processor achieves a CPI of 1.2?
We have the execution times of N*700ps*1 for single-cycle and N*260ps*1.2 for pipelined, where N is the number of instructions. The speedup is 2.24 (single-cycle time over pipelined time, N cancels out).