Problem Set Solutions/Mulitprocessing/Problem09

A simple shared-memory cache-coherent machine has four processors, no virtual-to-physical translation and 16-bit (physical) addresses. There is one L1 data cache per processor and there is no L2 cache. Each L1 cache is direct-mapped with four 64-byte blocks (the size of each cache is 256 bytes), and they are kept coherent using the MESI coherence protocol. The initial state of each cache is as follows (tags are shown in hexadecimal notation):


What happens if the following memory access is executed next. In particular, specify whether the access is a cache hit or a miss, is there a write-back, is there a broadcast on the shared bus as a result of this access, what (if anything) happens in each of the other caches as a result of the bus broadcast, where the data comes from (if not already in the cache), and what the new state of the block is in the requestor’s cache and why. For each part of this problem, start with the state of the cache shown above, not with the state left by prior questions.

P1 reads a word from address 0F4C


Offset is 0C, set is 1, tag is 0F. The line in set 1 has the wrong tag, so this is a miss. Because the existing line in set 1 is in state E, there is no write-back. The request for data is broadcast on the bus. No other cache has a matching line, so the shared line is not asserted and the memory responds with the data. When P1 cache receives the data, is puts it in set 1 (changing the tag to 0F) and sets its state to E