Problem Set Solutions/Mulitprocessing/Problem02

A simple shared-memory cache-coherent machine has four processors, no virtual-to-physical translation and 16-bit (physical) addresses. There is one L1 data cache per processor and there is no L2 cache. Each L1 cache is direct-mapped with four 64-byte blocks (the size of each cache is 256 bytes), and they are kept coherent using the MESI coherence protocol. The initial state of each cache is as follows (tags are shown in hexadecimal notation):


What happens if the following memory access is executed next. In particular, specify whether the access is a cache hit or a miss, is there a write-back, is there a broadcast on the shared bus as a result of this access, what (if anything) happens in each of the other caches as a result of the bus broadcast, where the data comes from (if not already in the cache), and what the new state of the block is in the requestor’s cache and why. For each part of this problem, start with the state of the cache shown above, not with the state left by prior questions.

P1 reads a word from address 0F8C


Offset is 0C, index is 2, tag is 0F. The (one) cache line in set 2 is invalid, so this is a miss and there is no write-back. P1’s cache does broadcast a request for this block on the bus. All other caches snoop this broadcast and P2’s cache finds that it has this block in an E state, so it changes its own state to S and asserts the bus Shared signal but lets the memory respond (or P2’s cache could respond with the data). P1’s cache gets the data and sets the state to S.