Assume having a two level memory hierarchy: a cache and a main memory, which are connected with a 32 bit wide bus. A hit in the cache can be executed within one clock cycle. At a cache miss an entire block must be replaced. This is done by sending the address (32 bits) to the memory which needs 4 clock cycles before it can send back a block by the bus. Every bus-transfer requires one clock cycle. The processor will need to wait until the entire block is in the cache. The following table shows the average miss ratio for different block sizes:
Which block size is the best one if the bus between the cache and the main memory is widened to 64 bits.
I. With the cost of the bus-arbitration of the previous two problems
II. Without the cost of the bus-arbitration of the previous two problems
I: Miss cost tm(B) = M(B)=100 * (1 + 4 + [B/8]) which gives us
tm(64) = 0:010 * (1 + 4 + 64/8) = 0:13 as the smallest value --> Bopt = 64
II: Miss cost tm(B) = M(B)=100 * (2 + 1 + 4 + [B/8]) which gives us
tm(128) = 0:0064 * (2 + 1 + 4 + 128/8) = 0:1472 as the smallest value --> Bopt = 128