Instruction Scheduling/Problem4

Schedule the following code using Tomasulo's algorithm assuming the hardware has three Load-units with a two-cycle execution latency, three Add/Sub units with 2 cycles execution latency, and two Mult/Div units where Mult has an execution latency of 10 cycles and Div 40 cycles. Assume the rst instruction (LD F6,34(R2)) is issued in cycle 1.

LD F6,34(R2)
LD F2,34(R3)
MULTD F0,F2,F4
SUBD F8,F6,F2
DIVD F10,F0,F6
ADDD F6,F8,F2

In which clock cycle (numbered 0,1,2,...) does the second LD instruction complete?

In which clock cycle does the MULTD instruction complete?

In which clock cycle does the ADDD instruction complete?

Solution

In which clock cycle (numbered 0,1,2,...) does the second LD instruction complete? 5

In which clock cycle does the MULTD instruction complete? 16

In which clock cycle does the ADDD instruction complete? 11