A processor is using a small PIPT (physically indexed physically tagged) write-back, write-allocate 32-byte cache with an LRU replacement policy. The cache is organized as two sets of two lines each and the physical address in this system only has 12 bits. In each part of this problem, you are given the type (read or write) and the physical address for the access, as well as the state of the cache before the access. For LRU counters, 0 indicates the least recently used block. Tags are shown in hex (base 16). You should fill out the state of the cache after the access and specify if this access is a hit or a miss and if there is a write-back as a result of the access. Note that each part of this problem is independent of the others – the state of the cache for each access depends only on the state before the access and the access itself.
Access: RD F18