A processor is using an 8K Byte 8-way set-associative L1 data cache with a 32-byte block size. This cache is virtually indexed and physically tagged, and the processor’s virtual address size is 64 bits but the physical address is only 48 bits.
If this is a write-back cache with a FIFO replacement policy, which other information must be kept (besides data and tags) for correct operation of this cache? How many bits (in total for the entire cache) are needed to keep this information?
We need a V (Valid) bit and a D (Dirty) bit for each line [-4 points if V bit omitted, -3 points if D bit omitted]. We also need 3 FIFO bits for each set (to keep track of which of 8 lines in the set is the next to replace) [-4 points if no bits for FIFO specified, -2 if using 3 FIFO bits per line instead of per set]. Overall, we need 2561+2561+32*3=608 bits for V, D, and FIFO. Together with tag bits, the number of non-data bits kept in the cache is 10336.