hpca/SampleMidterms/Midterm2/problem6

Problem 6. [25 points] TLBs and Caches

The processor has a 4KByte, direct-mapped, write-back, write-allocate, physically

indexed, physically-tagged data Ll cache with 256-byte blocks. It also has a fully

associative, 8-entry data TLB with the LRU replacement policy. The system uses 32-bit

virtual and physical addresses, with 4KByte pages.

A) [5 points] Can TLB and cache access be overlapped? Why?

B) [5 points] How is the address broken down for TLB and for cache access?

(What are the parts and which bits of the address belong to each part)

Screen Shot 2014-04-28 at 1.58.44 PM.png

C) [15 points] If both the cache and the TLB start out empty, and if the processor

executes the following sequence of accesses, determine for each access how its

address is broken down (in hex) and is it a hit in the cache hit and in the TLB:

Screen Shot 2014-04-28 at 2.00.45 PM.png Screen Shot 2014-04-28 at 2.01.13 PM.png