Problem 5. [15 points] ROB
A single-issue processor with a ROB is executing the following sequence of instructions
and, for each instruction, we show the cycle in which the instruction is fetched, decoded,
issued, begins to execute, and writes result. There is one adder and one multiplier and
only one CDB, and broadcast on this CDB takes an entire cycle. This is really the same
processor and instruction sequence as in Problem 4, except that a ROB has been added.
A) [3 points] For instructions I1-I5 in the table above, write-in the cycle in which
each instruction commits. Be careful, these five points are given on an all-or- nothing basis (you get all 5 points if and only if all 5 commit times are correct).
B) [4 points] If this processor had 8 reservation stations for the adder and 8 for the
multiplier, instructions I1 through I5 would still issue as shown above, but I6
would issue in cycle 9. What is size of the ROB? ______ entries. Explain:
C) [8 points] Suppose that, instead of completing normally, I4 detects an overflow
exception when it executes (in cycle 11). What happens in the next 5 cycles: