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**Problem 4. [20 points] Tomasulo’s Algorithm**

A single-issue processor uses Tomasulo’s algorithm in its floating-point unit, which has one adder and one multiplier, each with its own set of reservation stations. There is only one CDB, and broadcast on this CDB takes an entire cycle. The processor is executing the following sequence of instructions and, for each instruction, we show the cycle in which the instruction is fetched, decoded, issued, begins to execute, and writes result.

[2 points] What is the latency of the multiplier? _____. Explain:

[3 points] Is the multiplier pipelined (yes or no)? _____. Explain:

[4 points] How many reservation stations are there for the adder? _____. Explain:

[3 points] In which cycle does I6 begin to execute? _____. Explain:

[4 points] Which register does “??” represent in I7? _____. Explain:

[4 points] If the priority for using CDB depends on the type of instruction, between ADD and MUL the priority for using the CDB goes to ______. Explain: